According to the Cortex documentation at How to debug a HardFault on an ARM Cortex-M MCU | Interrupt it’s possible to turn off byte alignment (and division-by-zero) faults using the Configuration and Control Register (CCR) located at address 0xE000ED14. However, that address is not accessible from compiled C code (even reading from it crashes the device). Is the address space remapped in user code, or is it completely inaccessible?
1 Like
Considering the CCR allows access only in privileged modes, this makes sense since games on the Playdate run in unprivileged Thread mode.
Though I’m not sure why you’d need to configure this to begin with…
2 Likes
I wanted to save some space in my structs by packing uint8_t fields tightly (also it’s the default behaviour in GCC), but accessing fields which end up unaligned causes a crash. I can deal with it by just using wider types or padding, it just seems a bit wasteful.
1 Like